concurrent and conditional signal assignment (VHDL)

Question

In VHDL, there are two types for signal assignment:

concurrent   ---->    when...else
             ---->    select...when...else

sequential   ---->    if...else
             ---->    case...when

Problem is that some say that when...else conditions are checked line by line (king of sequential) while select...when...else conditionals are checked once. See this reference for example.

I say that when..else is also a sequential assignment because you are checking line by line. In other words, I say that there no need to say if..else within a process is equivalent to when..else. Why they assume when..else is a concurrent assignment?

Jim Lewis Jim Lewis · Accepted Answer · 2017-03-06T19:28:09

Where you are hinting at in your problem has nothing to do with concurrent assignments or sequential statements. It has more to do with the difference between if and case. Before we get to that first lets understand a few equivalents. The concurrent conditional assignment:

Y <= A when ASel = '1' else B when BSel = '1' else C ;

Is exactly equivalent to a process with the following code:

process(A, ASel, B, BSel, C) 
begin
  if ASel = '1' then
    Y <= A ;
  elsif BSel = '1' then 
    Y <= B ; 
  else 
    Y <= C ; 
  end if ;
end process ;

Likewise the concurrent selected assignment:

With MuxSel select
  Y <= A when "00", B when "01", C when others ;

Is equivalent to a process with the following:

process(MuxSel, A, B , C) 
begin
  case MuxSel is 
    when "00" =>    Y <= A; 
    when "01" =>    Y <= B ; 
    when others =>  Y <= C ;
  end case ; 
end process ;

From a coding perspective, the sequential forms above have a little more coding capability than the assignment form because case and if allow blocks of code, where the assignment form only assigns to one signal. However other than that, they have the same language restrictions and produce the same hardware (as much as synthesis tools do that). In addition for many simple hardware problems, the assignment form works well and is a concise capture of the problem.

So where your thoughts are leading really comes down to the difference between if and case. If statements (and their equivalent conditional assignments) that have have multiple "elsif" in (or implied in) them tend to create priority logic or at least cascaded logic. Where as case (and their equivalent selected assignments) tend to be well suited for things like multiplexers and their logic structure tends to be more of a balanced tree structure.

Sometimes tools will refactor an if statement to allow it to be equivalent to a case statement. Also for some targets (particularly LUT based logic like Xilinx and Altera), the difference between them in terms of hardware effiency does not show up until there are enough "elsif" branches though.

With VHDL-2008, the assignment forms are also allowed in sequential code. The transformation is the same except without the process wrapper.

concurrent and conditional signal assignment (VHDL)

2 Answers