an array declared as output reg with signals saved into multi flip-flop cannot coesist if the same array is delared into a different modue

Question

i've this arary(dout) that is passed into a module where there are 8 bit synchronous flip-flops, all works fine, but when i pass dout into another module(b_mux_write) as output reg [7:0] dout(i want to change the signals of dout into another module) is like broken, if i change output reg [7:0] dout to input[7:0] dout, all works fine, why?

//this module is just for declaring the clock and giving the signals 
//value to data, that are passed to the array dout, where every single element
// of dout correspond to a synchronous flip-flop
 module b_tb();
    reg clk;
    reg [7:0] data;
    wire [7:0] dout; 
    
  //Here i call the main module
    b_cpu b_cpu(
        data,
        dout

    );
    initial begin
        //initializing data, i know this is ugly, i'll make it more elegant in the future, i'm trying to create a processor :)
        data[0] = 1;
        data[1] = 1;
        data[2] = 1; 
        data[3] = 1; 
        data[4] = 1; 
        data[5] = 1; 
        data[6] = 1; 
        data[7] = 1; 
        
        clk = 1;

        $dumpfile("w.vcd");
        $dumpvars(0,b_tb);

    end 

always #1 clk = ~clk; //Here the clock switching from negative to positive
endmodule

    
//Main
module b_cpu(  
    //input clk ,
    input[7:0] data,
    input [7:0] dout
    );

    reg clk;
    
    fflop fflop(
        clk,
        data,
        dout
    );
    
    b_mux_read b_mux_read(
        clk,
        dout
    );
 

    b_mux_write b_mux_write(
        clk,
        dout
                 
    );
 
    initial begin
        clk = 1;
    end

    always #1 clk = ~clk;
    
    initial begin
        #2;
        $display("-----------cpu main begin-------");
        $display(dout[0]);
    end
endmodule
    
    module fflop(  
        input clk ,
        
        input[7:0] data,
        output reg[7:0] dout
        );
        
        //0;
        
        always@(clk) begin //LATCH DO1
            if(clk != 0)
                dout[0] <= data[0];
            else
                dout[0] <= 0;
           // $display(do1);
        end
         
        //1
        
        always@(clk) begin //LATCH DO1
            if(clk != 0)
                dout[1] <= data[1];
            else
                dout[1] <= 0;
           // $display(do1);
        end
    
        //2
        
        always@(clk) begin //LATCH DO1
            if(clk != 0)
                dout[2] <= data[2];
            else
                dout[2] <= 0;
           // $display(do1);
        end
    
        //3
    
        always@(clk) begin //LATCH DO1
            if(clk != 0)
                dout[3] <= data[3];
            else
                dout[3] <= 0;
           // $display(do1);
        end
    
        //4
    
        always@(clk) begin //LATCH DO1
            if(clk != 0)
                dout[4] <= data[4];
            else
                dout[4] <= 0;
           // $display(do1);
        end
    
        //5
    
        always@(clk) begin //LATCH DO1
            if(clk != 0)
                dout[5] <= data[5];
            else
                dout[5] <= 0;
           // $display(do1);
        end
    
        //6
    
        always@(clk) begin //LATCH DO1
            if(clk != 0)
                dout[6] <= data[6];
            else
                dout[6] <= 0;
           // $display(do1);
        end
    
        //7
    
        always@(clk) begin //LATCH DO1
            if(clk != 0)
                dout[7] <= data[7];
            else
                dout[7] <= 0;
           // $display(do1);
        end
    
        initial begin
           #1;
            $display("----flip-flop----");
            $display(dout[0]);
        end
    endmodule
    
//if i change output reg to input[7:0] dout the program works fine, but i need 
//the output reg, because i wan't to change the values of dout
module b_mux_write(input clk, output reg[7:0] dout);
endmodule

      
    module b_mux_read(input clk ,input[7:0] dout);
    endmodule

Serge Serge · Accepted Answer · 2021-07-27T17:16:24

Your dout signal serves as an input to the b_cpu module. The rule of thumb is that this signal can only be read inside this module. You should not try to assign a value to it.

Now, your b_mux_write module just does that, it assigns the value via the output port, which is of a reg type.

As a result, you drive the same signal from two ends: tb and mux_write. I believe that values you see are 'x's just because of this. You need to change your logic and and add some muxes to move your data in a correct direction.

Do not assign internally to 'inputs'. You can try to exploit 'inouts' but I do not think that you need it here.

an array declared as output reg with signals saved into multi flip-flop cannot coesist if the same array is delared into a different modue

1 Answers