Error: Assignment under multiple single edges is not supported for synthesis

2
votes

It is a four bit counter T flipflop design. Tflip module is used for each bit.

   module Tflip (q,t,clk,rst);
    output q;
    input t,clk,rst;
    reg q; //q output must be registered 
    always @ (posedge clk or negedge rst)
     if (rst <= 0)
       q <= 1'b0;
     else
       q <= t^q; // it is made up with X-OR gate.
  endmodule
1
verilog

1 Answers

1
votes

Synthesis tools require specific coding patterns, but you do not have a conventional reset condition. Change:

if (rst <= 0)

to:

if (!rst)

Perhaps your synthesis tool is confused because your code reads as:

if reset is less than or equal to 0

Synthesis tools also recognize the following patterns for active-low reset conditions:

if (~rst)

and:

if (rst == 0)