Binding interface to dut in top

Question

Please find my code on the edaplayground here: https://www.edaplayground.com/x/EDVr

In the top module, I am instantiating the dut and then am trying to bind an interface to the signals on it.

module tb_top;
  dut dut1();
  bind dut basic basic_intf(.clk(clk), .reset(reset), .addr(addr), .addr_out(addr_out));
  initial begin
    run_test("base_test");
  end  
endmodule

interface basic(
  input clk,
  input reset,
  inout [7:0] addr,
  inout [7:0] addr_out);
  
  modport dut(
    input clk,
    input reset, 
    input addr,
    output addr_out
  );
endinterface

// Code your design here

module dut(input logic clk, input logic reset, input logic[7:0] addr, output logic[7:0] addr_out);
  
  always_ff @(posedge clk) begin
    if(reset)
      addr_out <= 'h00;
    else
      addr_out <= addr;
  end
  
endmodule

The error I am getting is: Quote:

Error-[VIHIOP] Variable in high conn of inout port
testbench.sv, 144
dut, "clk"
This variable is not a net, it cannot be connected to an inout port.
Source info: : basic basic_intf( .clk (clk), .reset (reset), .addr (addr),
.addr_out (addr_out));

If I declare these signals as wire I will not be able to use <= operator in the driving function. I want to add that interface to config_db and retrieve it in the test. Test is a class of type uvm_test.

How do I resolve this?

You need to show the code for dut, because that is where you are binding your interface and where your problem is. — Matthew Taylor

Matthew Taylor Matthew Taylor · Accepted Answer · 2021-03-16T08:21:10

You are trying to instantiate (by binding) an interface with inout ports connected to variables with multiple drivers on those variables. (If you connect a variable to an inout or an output port, that port must be the only thing driving it.) addr is driven both by the input port and the interface instance; addr_out is driven both by the always block and the interface instance.

Binding interface to dut in top

1 Answers