How to modify bit bash sequence for write delays and read delays of DUT?

Question

I have a DUT were the writes takes 2 clock cycles and reads consume 2 clock cycles before it could actually happen, I use regmodel and tried using inbuilt sequence uvm_reg_bit_bash_seq but it seems that the writes and reads happens at 1 clock cycle delay, could anyone tell what is the effective way to model 2 clock cycle delays and verify this, so that the DUT delays are taken care.

Facing the following error now,

Writing a 1 in bit #0 of register "ral_pgm.DIFF_STAT_CORE1" with initial value 'h0000000000000000 yielded 'h0000000000000000 instead of 'h0000000000000001

Emman Emman · Accepted Answer · 2018-05-15T06:10:35

I have found one way of doing it, took the existing uvm_reg_single_bit_bash_seq and modified by adding p_sequencer and added 2 clock cycle delays after write and read method calls as per the DUT latency, this helped me in fixing the issue as well added a get call after write method to avoid fetching old value after read operation.

...
  `uvm_declare_p_sequencer(s_master_sequencer)

         rg.write(status, val, UVM_FRONTDOOR, map, this);
         wait_for_clock(2); // write latency
         rg.read(status, val, UVM_FRONTDOOR, map, this);
         wait_for_clock(2); // read latency
         if (status != UVM_IS_OK) begin
            `uvm_error("mtm_reg_bit_bash_seq", $sformatf("Status was %s when reading register \"%s\" through map \"%s\".",
                                        status.name(), rg.get_full_name(), map.get_full_name()));
         end

         val = rg.get(); // newly added method call (get) to fetch value after read
...

   task wait_for_clock( int m = 1 );
      repeat ( m ) begin
      @(posedge p_sequencer.vif.CLK);
      end
    endtask: wait_for_clock
...

How to modify bit bash sequence for write delays and read delays of DUT?

1 Answers