I have an system verilog interface
interface XZY(input clk, input reset, input a, output b);
clocking cb @(posedge clk);
input a;
output b;
endclocking: cb
modport master(clocking cb, input reset);
endinterface: XYZ
I am passing the interface as virtual interface to my driver.
The driver is using the moport(master).
Now I need to access both the posedge and the negedge of the clock in my driver.
I can easily access the posedge by @cb.
How do I access the negedge?
Do i need to create another modport/clocking block for the negedge and pass it separately to the driver?