Systemverilog modport access to interface clk without being declared as input

Question

I see different examples online of using modports for interfaces when there are port inputs on the interface. Should modports include clk and reset on the modport even though they are interface inputs?

Here's an example with clk not included on modport : https://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/ Section: Modports in Interfaces

Putting clk in the modport gives a Spyglass lint error (undriven variable), here's a general idea of the error:

interface MY_IF (input clk);
signal my_sig;
modport master (input clk, my_sig);
endinterface

MY_IF if (.clk(clk));

MY_MOD (.my_if(if.master)); // claims clk is undriven

Whereas Cadence gives issues if the clk is missing and I pass a virtual interface into a class where I use clk.

Which way is correct? Does a modport have to have ALL of the signals listed, or are port interface signals always available?

is clk in the interface instance port driven by anything? your example is missing any driver. — Serge

Karan Shah Karan Shah · Accepted Answer · 2019-07-16T17:28:16

You can include interface ports in modports. But just that the port direction (input, output, inout) can't be changed in modports.

Here is one example.

interface simple_bus (input logic clk);
  logic req, gnt;
  logic [7:0] addr, data;
  logic [1:0] mode;
  logic start, rdy;

  modport slave (input req, addr, mode, start, clk, 
                 output gnt, rdy,
                 ref data);

  modport master(input gnt, rdy, clk,
                 output req, addr, mode, start,
                 ref data);
endinterface: simple_bus

Systemverilog modport access to interface clk without being declared as input

2 Answers