How to fix 'port multiply driven' warnings System Verilog

Question

I have an AXI UVC which can be configured to be either Master or Slave and an interface with 3 clocking blocks (mst_cb, slv_cb, mon_cb). I get warning messages telling me that a port is multiply driven. How do you fix these warning messages?

I'm not sure but I think the problem lies with the ports having different directions depending on the clocking block used (i.e AWREADY is an input for Master and output for Slave).

interface axi_if();
  logic aclk;
  logic awready;

  clocking mst_cb @(posedge aclk);
     input awready;
  endclocking

  clocking slv_cb @(posedge aclk);
    ouput awready;
  endclocking

endinterface

I tried to temporarily remove the Slave clocking block and the warning messages were gone. However, I need the Slave clocking block for when the UVC is configured as a Slave.

most likely your awready is driven by something else in the model. Find what it is and figure out what you want to do. In general you should not drive the same variable multiple times. — Serge

dave_59 dave_59 · Accepted Answer · 2019-04-11T13:32:28

Most likely this is because someone has a continuous assignment to aready. Change the declaration to a wire.

How to fix 'port multiply driven' warnings System Verilog

1 Answers