I'm getting this error for my verilog code, “Illegal operation for constant expression”

1
votes

I am getting error for the below piece of code:

same error is coming for state_check_core

assign state_check_core = (post_vinout_force0_1p5.v_eq >=0.675 & post_vinout_force0_1p5.v_eq <= 0.825) ? 1'b1 : 1'b0;
assign state_check_dgo = (post_vinout_force0_1p5.v_eq >=1.35 & post_vinout_force0_1p5.v_eq <= 1.65) ? 1'b1 : 1'b0;
//setting the outputs
wire out_limit;
if(state_check_dgo==1'b1) begin
assign out_limit = ((vdd_1p5.v_eq>=1.35 & vdd_1p5.v_eq<=1.65) & (vdd_main>=0.675 & vdd_main<=0.825) & (vss==0.00)  & ((post_vinout_sense0_1p5.v_eq>= 1.35 & post_vinout_sense0_1p5.v_eq<= 1.65 ) & (post_vinout_sense1_1p5.v_eq>= 1.35 & post_vinout_sense1_1p5.v_eq<= 1.65)) & (i_force0 >= 1.35e-03 & i_force0 <= 1.65e-03) & (i_force1 >= 1.35e-03 & i_force1 <= 1.65e-03) & (i_1p5 >= 3.5e-03 & i_1p5 <= 4e-03)) ;
end

ERROR:

if(state_check_dgo==1'b1) begin
                 |
xmvlog: *E,NOTPAR (../a_ip_post_imx_ts_cln5p.v,184|17): Illegal operand for constant expression [4(IEEE)].
    if(state_check_core==1'b1)
1
verilogsystem-verilog
This is a duplicate of stackoverflow.com/questions/63463776/… - dave_59

1 Answers

0
votes

The if needs to be inside an always block; otherwise, the simulator thinks you are using a generate, which expects state_check_dgo to be a constant (like a parameter).

In this case, you would not have an assign inside an always block, and you need to change out_limit from wire to reg.

reg out_limit;
always @* begin
    if (state_check_dgo==1'b1) begin
        out_limit = ((vdd_1p5.v_eq>=1.35 & vdd_1p5.v_eq<=1.65) & (vdd_main>=0.675 & vdd_main<=0.825) & (vss==0.00)  & ((post_vinout_sense0_1p5.v_eq>= 1.35 & post_vinout_sense0_1p5.v_eq<= 1.65 ) & (post_vinout_sense1_1p5.v_eq>= 1.35 & post_vinout_sense1_1p5.v_eq<= 1.65)) & (i_force0 >= 1.35e-03 & i_force0 <= 1.65e-03) & (i_force1 >= 1.35e-03 & i_force1 <= 1.65e-03) & (i_1p5 >= 3.5e-03 & i_1p5 <= 4e-03)) ;
    end
end