Declaration of random packed associative array

1
votes

I wrote a code to initialize an packed associative array in the following fashion. 

int              msize  = $urandom_range(20)            ;


bit  [0:3]      [0:msize]   mem     [int]               ;

But, it is showing error like : "Illegal operand for constant expression"
What is the alternative for this one.

2
associative-arraysystem-verilog

2 Answers

3
votes

The dimensions of the packed portion of an array must be a constant, decided at compile time. The assignment of msize is decided at run time. Make msize a parameter assigned at compile time.

Alternatively, if you want mem to have a random msize at run time, then mem should be defined as:

bit [0:3] mem [int] [];

Before accessing any element you should put:

if(!mem.exists(lookup_id)) mem[int_key_address] = new[msize];

Read all about arrays in SystemVerilog in ยง 7 of IEEE Std 1800-2012, it is free from IEEE the website.

0
votes

you can define the array as rand and use the constraint: 

  rand msize    
  rand bit  [0:3] mem [int] []

then in a constraint:
msize inside [5:10]
foreach(mem[idx]) mem[idx].size == msize
on a side note the seed used in $urandom is the different from the system verilog seed so if you use $urandom the test won't reconstruct