Convert std_logic_vector to enum type in VHDL

Question

I want to create verilog testbench for the vhdl designs but my vhdl design source contains some enum type cannot accept by Vivado's mixed language boundary Ref. So I create a VHDL wrapper to convert enum type to std_logic_vector type or convert std_logic_vector to enum type. There are some elegant way to converting enum type to std_logic_vector Convert enum type to std_logic_vector VHDL. But How to converting std_logic_vector to enum type in VHDL?

If you dont want to use an integer conversion (as per @Renaud's answer), they you will need to manually define all the encodings for your enum for the encoding. — Tricky

Renaud Pacalet Renaud Pacalet · Accepted Answer · 2020-08-06T08:02:15

As you are mentioning Vivado I guess you are more interested in synthesis semantics than simulation semantics. I will thus assume that your std_logic_vector objects carry information that can be considered as the binary representation of integers, and that you are not interested in std_logic values other than '0' and '1'.

To convert std_logic_vector values to an enumerated type you will first need a large enough enumerated type. So, if your vectors are N bits long you will need a 2^N values enumerated type, for instance, if N=16:

type s2e_t is (s2e0, s2e1,... , s2e65535);

(lot of typing but as you asked for it...) Then, you can simply convert your vector values to non-negative integer values and pick the corresponding enumerated type value with the val type attribute (dual of the pos attribute):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
type s2e_t is (s2e0, s2e1,... , s2e65535);
signal e: s2e_t;
signal s: std_logic_vector(15 downto 0);
...
e <= s2e_t'val(to_integer(unsigned(s));

Convert std_logic_vector to enum type in VHDL

1 Answers