verilog wrapper around systemverilog intefaces with inout ports

Question

I just downloaded a behavioral model of a DDR4 interface from micron. To my surprise, they converted the ports entirely to a system interface, which creates a problem when interfacing this model to a mixed language simulation of Verilog or VHDL.

My question is this. How to create a verilog or VHDL wrapper around a DDR4 SystemVerilog interface that contains inout ports? Here's an example of what I'm trying to do:

//SystemVerilog Interface
interface micron_ddr4_if();
   wire [7:0]  DQ;
   wire        DQS_t;
   wire        DQS_c;

   modport  system (inout DQ, DQS_t, DQS_c);

endinterface

// System Verilog Module
module micron_ddr4_model(
    micron_ddr4_if  ddr4_if
);
    // ...
endmodule

// Convert SystemVerilog Interface into Verilog Interface
module my_verilog2001_wrapper(
   inout wire [7:0]  DQ,
   inout wire        DQS_t,
   inout wire        DQS_c
);
   micron_ddr4_if     ddr4_if();

   micron_ddr4_model  ddr4_model(ddr4);

   // How to connect this part?
   //
   //   DQ      <=> ddr4_if.DQ;
   //   DQS_t   <=> ddr4_if.DQS_t;
   //   DQS_c   <=> ddr4_if.DQS_c;
   //
endmodule

Answer 1

You can use port expressions. People see this syntax on module instances but don't realize they can also use it in port declarations.

module my_verilog2001_wrapper(
   inout .DQ(ddr4_if.DQ),
   inout .DQS_t(ddr4_if.DQS_t),
   inout .DQS_c(ddr4_if.DQS)
);
   micron_ddr4_if     ddr4_if();

   micron_ddr4_model  ddr4_model(ddr4_if);

endmodule

Answer 2

tri [7:0] tri_DQ;

assign tri_DQ     = DQ;
assign tri_DQ     = ddr4_if.DQ;
assign DQ         = tri_DQ;
assign ddr4_if.DQ = tri_DQ;