VHDL inout ports

Question

I am having trouble creating an entity using inout ports. I tried writing the following code where A is an input and B is an output and it works fine. But as soon as I change A to an inout port, it implements but it won't simulate. Can anyone tell me what the problem is?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Problem2 is
Port ( A : inout  integer;
       B : out  integer
          );
end Problem2;

architecture Behavioral of Problem2 is

procedure change (signal A: inout integer; signal B: out integer) is 
begin
B<=A after 20 ns;
end change;

begin

change(A=>A, B=>B);

end Behavioral;

Don't these kind of questions belong on electronics.stackexchange? — blueshift
@blueshift VHDL is can be argued to be a programming language. Should be fine her. — Philippe
"..but it won't simulate" doesn't help us much - won't it elaborate? Or does it run, but not do what you expect, in which case, tell us what it does and what you expected? — Martin Thompson

wjl wjl · Accepted Answer · 2012-04-02T04:52:02

The procedure "change" is a driver on A, but doesn't explicitly drive anything, so A will be driven to 'U'. Try this change which should do what you seem to expect:

procedure change (signal A: inout integer; signal B: out integer) is 
begin
  A <= 'Z';
  B <= A after 20 ns;
end change;

VHDL inout ports

3 Answers