Generate ports in VHDL?

Question

Is there a way to generate port declarations in VHDL? I would like to do something similar to #IFDEF for debug signals out to pins for an oscope. That way I can quickly enable or disable debug logic. For example:

entity my_entity is
port (  

    debug_label: if debug_on = 1 generate
    debug1: out;
    end debug_label;

    ....

    );
end component;

When I try something like this is doesn't work. Is there any way to make it work? Or an alternative way to do something similar?

If you're adventurous you could use m4 to add macros to your code. It would require some care, though, to ensure that your tools only see the post-processed source. This is the type of problem m4 is designed to solve. — Kevin Thibedeau
To save wiring through the hierarchy, have you considered using an impure function instead of ports to communicate the debug information? See github.com/chiggs/hidden_wires for a synthesisable example in SystemVerilog. — Chiggs

Morten Zilmer Morten Zilmer · Accepted Answer · 2014-04-28T19:59:03

The ports can't be conditional, but the length of for example a std_logic_vector can be configurable through a generic, and the length may even be 0, resulting in null range. An entity showing this is:

entity mdl is
  generic(
    DEBUG_LEN : natural := 0);
  port(
    ...
    debug_o : out std_logic_vector(DEBUG_LEN - 1 downto 0));
end entity;

You should run a test synthesis to see how the your selected synthesis tool handles null range when assigning to pins.

Generate ports in VHDL?

1 Answers