Interrupt Controller's In-Service Register bits when a non-maskable interrupt occurs

Question

I have the following question (regarding x86 architecture):

What happens when a non-maskable interrupt (e.g. NMI) interrupts a maskable interrupt which is in progress? Does the corresponding ISR (In-Service Register) flag of the pre-empted interrupt remains set in the interrupt controller's ISR register when the maskable interrupt is served or all the bits in the In-Service Register are getting cleared?

Thanks in advance.

Answer 1

In the original IBM PC hardware design, the NMI signal did not involve the interrupt controller in any way, so it would have no effect on the in-service register. Though it's some 30 years later, my guess is this is still the case; modern chip makers more or less have their hands tied by these kinds of core legacy behaviors.

Answer 2

The ISR must be cleared in the interrupt handler by sending EOI command (end of interrupt) to the interrupt controller.