What happens if 'interrupt' and 'trap' both the flag bits are set in a microprocessor?

2
votes

In an x86 microprocessor, there is a flag register having a 'trap bit'--when set, it causes the microprocessor to trap to an exception handler after every instruction. Then there is an 'interrupt bit' which, when set, enables interrupts and redirects to ISR. What happens when both of them are set simultaneously and an interrupt is received?

2
x86interruptcpu-registersflagsmicroprocessors
EFLAGS is a register. It isn't part of an execution unit that can perform an integer multiply, or a vector shuffle, or any other kind of execution unit. – Peter Cordes
IF (the bit in EFLAGS) merely allows external interrupts (like keyboard or timer). Are you asking what happens when there actually is an interrupt pending, other than the trap bit? – Peter Cordes
@PeterCordes Yes. – Khodkumbhe Awani Ramdas

2 Answers

2
votes

The Intel SDM, volume 3, section 6.9, lists the relative priorities of simultaneous exceptions and interrupts. For the case you have asked about, Debug Trap Exceptions are priority 4, and Maskable Hardware Interrupts are priority 6. Thus the debug trap will be serviced.

If the debug exception descriptor in the IDT is a trap gate, the pending interrupt will be serviced at the next instruction boundary. If the descriptor is an interrupt gate, the IF flag is cleared as part of exception processing, so the interrupt will remain pending until IF is set to 1.

In any case, the Trap Flag is cleared as part of interrupt or exception processing, so debug traps do not occur during the interrupt or exception handler.

-2
votes

With relation to the process itself, traps will beat interrupts since they stop the process dialog. But at the start they are both invoked simultaneously. The only difference is that interrupts allow the process to continue execution.