Unsuccessful assignment in SystemVerilog

Question

I write ldpc_if.sv and ldpc_transaction.sv as follows.

"ldpc_if.sv"

interface ldpc_if#(parameter COLS=9216, parameter ROWS=1024) (input clk, input reset);
  logic [COLS-ROWS-1:0] en_enq_data;
  logic                 en_enq_valid;
  logic                 en_enq_ready;

  logic [ROWS-1:0]      en_deq_data;
  logic                 en_deq_valid;
  logic                 en_deq_ready;

  logic [COLS-1:0]      de_enq_data;
  logic                 de_enq_valid;
  logic                 de_enq_ready;

  logic [COLS-1:0]      de_deq_data;
  logic                 de_deq_valid;
  logic                 de_deq_ready;

 endinterface

"ldpc_transaction.sv"

class ldpc_transaction#(parameter WIDTH=8192) extends uvm_sequence_item;
  rand bit [WIDTH-1:0] data;

  bit [8191:0]  encode_data_in;
  bit [1023:0]  encode_data_out;

  bit [9215:0]  decode_data;

  `uvm_object_utils(ldpc_transaction)

  function new(string name = "ldpc_transaction");
    super.new();
  endfunction
endclass

And I write ldpc_monitor.sv to monitor interface.

task ldpc_monitor::collect_one_pkt(ldpc_transaction tr);
  while(1) begin
  @(posedge vif.clk);
  if(vif.en_enq_valid && vif.en_enq_ready) break;
  end

  tr.encode_data_in <= vif.en_enq_data;

  while(1) begin
    @(posedge vif.clk)
    if(vif.en_deq_valid && vif.en_deq_ready) break;
  end

  tr.encode_data_out <= vif.en_deq_data;

 while(1)begin
   @(posedge vif.clk)
   if(vif.de_deq_valid && vif.de_deq_ready)begin
     break;
   end
 end
 tr.decode_data <= vif.de_deq_data;
 $display("tr.decode_data = %0h", tr.decode_data);
 $display("vif.de_deq_data = %0h", vif.de_deq_data);
endtask

vcs compiles all files successfully. However, tr.decode_data is always displayed as zero. But, vif.de_deq_data is correct. Why is vif.de_deq_data not assigned to tr.decode_data.

Svetlomir Hristozkov Svetlomir Hristozkov · Accepted Answer · 2020-05-30T10:51:37

It's because the $display you've used to display your transaction is blocking. Conversely, you've used an non-blocking assignment to set tr.decode_data.

Thus, your $display statement actually gets executed before your assignment. Getting a 0 is just an artefact of your simulator - could be any random stuff in the memory assigned to that variable (though most simulators just reset to 0).

Quick search revealed this useful example which illustrates exactly your problem.

https://verificationguide.com/systemverilog/systemverilog-nonblocking-assignment/

Unsuccessful assignment in SystemVerilog

1 Answers