Randomly select items from a SystemVerilog queue

Question

I have a queue of registers that I instantiate with the registers in the memory map. What happens is that some of these registers will be written into directly using RAL, and others will be written through another method. My test is supposed to randomize the number and names of the two sets of registers each time. How can I randomize the number and names of the registers to be selected for each configuration without duplicating?

The result can be any format that will allow me to use these registers, so if it results in two sub-queues it would be fine.

EDIT:

So I can have a queue like this: reg_queue = {reg_item1, reg_item2, reg_item3, reg_item4, reg_item5, reg_item6}

And I want to randomly select a number of these registers to write to using say Method A, and the rest will be written to using Method B.

So I may end up having 2 queues: reg_queue_a = {reg_item3, reg_item1, reg_item4, reg_item5) and reg_queue_b = {reg_item2, reg_item6}

Can I do this with a shuffle or something?

You should certainly know how to generate random numbers to use as an index into the queue. But there must be more to your problem that you are not explaining. It would help to show what the code would look like if you manually selected the registers. — dave_59
Yes, I can select random items from the queue, but I want to also separately select the items that haven't been selected in the first phase. I'll edit the question to explain further. — Mahmoud Abdelgawad

dave_59 dave_59 · Accepted Answer · 2021-04-22T19:59:21

You can add a constraint the size of the sum of the two queues to be the size of the original queue.

rand int unsigned reg_queue_a[$], reg_queue_b[$]; // queue of index values
constraint queue_size { reg_queue_a.size() + reg_queue_b.size() == reg_queue.size();
                        // range if needed
                        reg_queue_a.size() inside {[1:reg_queue.size()-1]};
                      }
constraint queue_uniq { foreach (reg_queue_a[i]) reg_queue_a[i] inside {[0:reg_queue.size-1]};
                        foreach (reg_queue_b[i]) reg_queue_a[i] inside {[0:reg_queue.size-1]};
                        unique {reg_queue_a,reg_queue_b};
                      }

Randomly select items from a SystemVerilog queue

1 Answers