Verilog - masking using 1 bit input

0
votes

I have a situation I'm not sure what's the right syntax that exists which can solve it. In my code I have

reg [N-1:0] bit_list;

and another variable n which counts how many bits I inserted into bit_list. Occasionally and according to the input - I need to, during a single posedge, shift bit_list by 1 then change bit_list[N-n] to my input. My idea was I can do the following

bit_list<=bit_list<<1 || X

Where X should be replaced some N-1 long vector that has zeros in all bits except for N-n. The problem is I don't know to describe such a vector - Hence my question. I'm sure my problem is simple enough to be solved in a variety of simple ways, so any solution to my problem will work.

Sorry if my question is noobish as I'm still new, help will be appriciated of course.

1
verilog

1 Answers

0
votes

You can use a mask. (BTW || is logical-or, you want | a bitwise-or)

reg [N-1:0] mask;

mask = ({ {N{1'b0}},1'b0}) << n) - 1; // the concat is needed in case N > 32

bit_list<=((bit_list<<1) & ~mask) | (X & mask);