Verilog select bit depending on input

0
votes

I am writing a behavioral verilog module where a different bit is selected based upon one of the input variables. I wrote the following code to reference the 3-S position in the D vector:

module Part4(input [3:0] D, input [1:0] S, output F);
    always @(D, S)
        F = D[3-S];
endmodule

This gives the following errors: "ERROR:HDLCompilers:247 - "Part4.v" line 5 Reference to scalar wire 'F' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "Part4.v" line 5 Illegal left hand side of blocking assignment"

How do I go about selecting a different bit based upon the input S?

1
verilog

1 Answers

2
votes

If F is a wire, then you can't assign to it inside an always @ block. Either change it to a reg, or do the assignment outside of an always @ block like this:

module Part4(input [3:0] D, input [1:0] S, output F);
    assign F = D[3-S];
endmodule