include VHDL package in SystemVerilog Testbench

0
votes

I have this Systemverilog testbench, in which I want to use a package written in VHDL. When I do: 'include "desired_pkg.vhd", it appararantly interpretes is a Verilog package, as ModelSim reports: 

Error: (vlog-13069) ** while parsing file included at C:/Users/VHDL/CO_code/CO_18_03/simulation/ed_sim/models/tb_top.sv(22)
** at C:/Users/VHDL/CO_code/CO_18_03/CO_simulation/mentor/020_regmaps_struct_pkg.vhd(1): near "--": syntax error, unexpected --, expecting class.

So it tries to interpret -- (comment in VHDL) as something in Verilog. How to include this package without rewriting it into Verilog?

2
packagevhdlsystem-verilog

2 Answers

2
votes

you dont use include as that is a pre-processor directive, and assumes the included code is verilog. You need to import the code:

import vhdl_lib::desired_pkg::*

But be aware, importing VHDL from verilog is not defined by any standard, and is purely down to the tool whether it even works, and what items in the package are supported.

0
votes

Thanks. It works with Modelsim.

In the seek of completeness, let me add some details below:

  • I compiled the Vhdl package with -mixedsvvh
  • I also added -mixedsvvh when compiling my SystemVerilog module
  • I added import my_pkg::*; at the beginning of my SystemVerilog module file
  • beware of case: it seems all variables are imported in low case (I mean, sometimes people are used to define Vhdl constants in HIGH_CASE but if you copy paste as is in your SystemVerilog, you will get "Undefined Variable")

My two cents ;)