SystemVerilog parameterized functions in Quartus II

Question

I have the following code, file c.sv:

virtual class C#(parameter W = 32); // line #2 where error message points
    static function logic [W-1 : 0] f(input logic [W-1 : 0] in);
        return ~in;
    endfunction
endclass

I then call it from top.sv:

`include "c.sv"
module top(input wire [3:0] key, ouptut wire [3:0] led);
    assign led = C#(4)::f(sw);
endmodule

In ModelSim 10.3d it works fine, but Quartus II x64 15.0.1 build 150 reports this error after Analysis & Synthesis:

Error (10170): Verilog HDL syntax error at c.sv(2) near text "virtual"; expecting a description

If I comment out inlcude "c.sv" and replace function call with a simple ~led then it works in the dev board.

What am I doing wrong?

Chiggs Chiggs · Accepted Answer · 2015-09-09T07:02:46

Sadly, there is no way currently to support parameterised functions in Altera Quartus. You have the following courses of action available:

Raise a support ticket with Altera
Use a third-party synthesis tool and feed the netlist into Quartus
Re-factor your code to be less generic

Option 2 will of course involve forking out a non-trivial sum of money. Synopsys Design Compiler supports this construct, your mileage may vary with other tools.

For option 3 you could resort to macros, generated code or optional file compilation to achieve a similar result.

It's somewhat depressing that this capability isn't available to Altera FPGA users. For the benefit of the community please raise a ticket regardless of the course of action you choose. The more demand there is, the more likely Altera are to implement this feature.

There is some more discussion and prototyping of possible work-arounds that don't involve classes on the "Width independent functions" question.

SystemVerilog parameterized functions in Quartus II

1 Answers