Why Quartus Prime does not want to ignore systemverilog assertion used for simulation?

Question

I have following property declaration and check in one of my system verilog files:

   property StepOutP_pulse_width;
      int count;
      @(posedge ClkRs_ix.clk)
    ($rose(mc.outvec.StepOutP_o),count=STEPPER_PULSE_WIDTH) |->
      (mc.outvec.StepOutP_o,count--)[*] ##1 (~mc.outvec.StepOutP_o && count==0);
   endproperty // StepOutP_pulse_width
   assert property (StepOutP_pulse_width);

This basically checks the width of a pulse generated by signal mc.outvec.StepOutP_o

When I try to compile the design, Quartus Prime fails on this property declaration saying

Error (10170): Verilog HDL syntax error at steppingcontroller.sv(404) near text: "]"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Now, I would be thinking, that during analysis&synthesis these property declarations and associated assertions are completely ignored as they only concern simulation. But apparently it is not the case. Modelsim (original mentor graphics version) does not have a problem to compile it, and as well the assertion does what is expected. Quartus verilog compilation settings are set to 'SystemVerilog'

How to:

make the property specification compliant with quartus compiler?
or setup compiler to ignore these assertions?

Thanks

all methodology i've been working with suggest putting ifdef/ifndef around assertion code. So, you can do it. It is preferred over using translate on/off directives. — Serge
The error message suggests it is treating the file as Verilog instead of SystemVerilog. If you comment out the assertions, do it accept other SystemVerilog keywords such as always_comb and always_ff? — Greg
I have checked, and Quartus compiler is really setup in SystemVerilog mode. Unless there is another setting than Assignments/Settings/Compiler Settings/Verilog HDL input. What is exact reason why ifdef should be prefered method over on/off directives? — David Belohrad

Pulimon Pulimon · Accepted Answer · 2017-10-26T00:01:58

One way to solve this is to use synthesis directives. You can specify synthesis translate_off and synthesis translate_on as shown below:

// synthesis translate_off    
property StepOutP_pulse_width;
      int count;
      @(posedge ClkRs_ix.clk)
    ($rose(mc.outvec.StepOutP_o),count=STEPPER_PULSE_WIDTH) |->
      (mc.outvec.StepOutP_o,count--)[*] ##1 (~mc.outvec.StepOutP_o && count==0);
   endproperty // StepOutP_pulse_width
   assert property (StepOutP_pulse_width);    
// synthesis translate_on

Any code written between the translate_off , translate_on comments is ignored by the compiler. Please note that this feature can be disabled/enabled by setting the option ignore_translate_off_and_synthesis_off

Why Quartus Prime does not want to ignore systemverilog assertion used for simulation?

1 Answers