HDMI and Pixel Clock | FPGA

Question

Hej,

I would like to get a HDMI Signal out of my Spartan 7(FPGA).
Resolution: 640 x 480 @ 60 Hz with 25.2MHz for my Pixel Clock.
That means i will have in total (with blanking time) 800 x 525 @ 60.0 Hz

But how does the monitor know which clock is the first one?
In HDMI there isn't something like hsync and vsync as in VGA, right?

So for example, if i run my data over HDMI und connect the monitor after that.
How tf knows the monitor the next frame starts?

Just 4 interested here is the code ->

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

Library UNISIM;
use UNISIM.vcomponents.all;

entity Takt is
    Port ( 
    CLK100MHZ             : in  STD_LOGIC;      -- Pin R2
    clk_out_p             : out STD_LOGIC;      -- Pin L18 (1)
    clk_out_n             : out STD_LOGIC;      -- Pin L17 (2)
    clk_out_25Mhz         : inout STD_LOGIC;    -- Pin M14 (3)
    clk_out_250Mhz        : out STD_LOGIC;      -- Pin N14 (4)
    controll_LED          : out STD_LOGIC       -- Pin E13 (LED4)
    );

end Takt;

architecture Behavioral of Takt is

    signal locked       : std_logic;

-- init clock
--25.20 MHz    800 x 525 @ 60.000000000 Hz    (exact) <-- go with that
--25.20 MHz    840 x 500 @ 60.000000000 Hz    (exact)
component myclock
port
 (-- Clock in ports
  clk_in1           : in     std_logic;
  -- Clock out ports
  clk_out1          : out    std_logic;
  clk_out2          : out    std_logic;
  -- Status and control signals
  reset             : in     std_logic;
  locked            : out    std_logic
 );
end component;

begin
--Controll LED einschalten
    controll_LED <= '1';

-- Erzeugen der ClockSignale durch pregenerated Code by clockingWizard tool by Xilinx
clock_inst : myclock
   port map ( 
  -- Clock out ports  
   clk_out1 => clk_out_25Mhz,
   clk_out2 => clk_out_250Mhz,
  -- Status and control signals                
   locked => locked,
   reset => '0',
   -- Clock in ports
   clk_in1 => CLK100MHZ
 );

 -- via OBUFDS buffern des signals und aufsplitten auf clk_p und clk_n
OBUFDS_inst : OBUFDS
   generic map (
      IOSTANDARD => "DEFAULT", -- Specify the output I/O standard
      SLEW => "SLOW")          -- Specify the output slew rate
   port map (
      O => clk_out_p,          -- Diff_p output (connect directly to top-level port)
      OB => clk_out_n,         -- Diff_n output (connect directly to top-level port)
      I => clk_out_25Mhz       -- Buffer input 
   );

--nach Xilinx ist DDR nötig wenn aus "externen" Speicher gelesen wird

end Behavioral;

rhall rhall · Accepted Answer · 2019-11-16T08:26:48

When you ask about the "first clock" i assume you mean the first Pixel of an image. Your assumption that there is no VSYNC or HSYNC transmitted via HDMI is also wrong.

You should have a look at 3 important things minimum: HDMI, DVI and TDMA.

The TDMA link points to Wikipedia and you'll find HDMI and DVI linked there as well. You need to understand them before you try to implement a HDMI transmitter.

Your code is missing a lot of things like data lanes, TDMA encoders, an actual data source, etc. You might want to think about just using a HDMI IP which is afaik included in Vivado.

HDMI and Pixel Clock | FPGA

2 Answers