Lattice Fpga Internal clock

Question

I'm trying to configure a lattice MachX03's internal Oscillator. I read the MachXO3 sysCLOCK PLL Design and Usage Guide* and tried using the vhdl code found on page 31 of the documente, but I keep getting this error (VHDL-1261) syntax error near COMPONENT. Can someone tell me how I can get the clock to work using VHDL? here is the code I'm trying to use:

LIBRARY lattice;

library machXO3;
use machXO3.all;

COMPONENT OSCH
   GENERIC(
         NOM_FREQ: string := "53.20"); --53.20MHz, or can select other supported frequencies
   PORT(
         STDBY    : IN  STD_LOGIC;     --'0' OSC output is active, '1' OSC output off
         OSC      : OUT STD_LOGIC;     --the oscillator output
         SEDSTDBY : OUT STD_LOGIC);    --required only for simulation when using standby
END COMPONENT;


OSCInst0: OSCH
   GENERIC MAP (NOM_FREQ  => "53.20")
   PORT MAP (STDBY => '0', OSC => clk, SEDSTDBY => OPEN);

and here is the code found in the manual:

library machXO3;
use machXO3.all;

COMPONENT OSCH
-- synthesis translate_off
  GENERIC (NOM_FREQ: string := "2.56");
-- synthesis translate_on
  PORT (STDBY:INstd_logic;
          OSC:OUTstd_logic;
     SEDSTDBY:OUTstd_logic);
END COMPONENT;

  attribute NOM_FREQ : string;
  attribute NOM_FREQ of OSCinst0 : label is "2.56";

begin
OSCInst0: OSCH
-- synthesis translate_off
  GENERIC MAP( NOM_FREQ => "2.56" )
-- synthesis translate_on
  PORT MAP (STDBY=> stdby,
  OSC => osc_int,
  SEDSTDBY => stdby_sed
);

*http://www.latticesemi.com/view_document?document_id=50124

A component is not a top level item. You need to instantiate the component in the architecture of am entity. And of you don't know what I'm talking about, you should really lookup some VHDL tutorial on the interwebs. — JHBonarius
Thanks, After reading JHBonarius, I saw the mistake I was making and fixed my code and it ended up working thanks for helping guys — user169808
It might be useful for other people searching for an example how to use the internal oscillator, if you could just write an answer with a little working example where you instantiate the oscillator component and e.g. blink a LED. Yes, you can answer your own questions. — Frank Buss

user169808 user169808 · Accepted Answer · 2019-02-23T02:22:40

to Use the internal Osc basically use the code in the menu, mentioned above. to get a simple osc working write the following in vhdl. the code sets up a 2.56 Mhz clock, the slowest the internal clock can generate. the highest frequency the interal generator can output is 133 Mhz, refer to pages 30-20 of the document http://www.latticesemi.com/view_document?document_id=50124

library  ieee;
use  ieee.std_logic_1164.all;

-- For Main Clock --
library machXO3l;
use machXO3l.all;
--------------------

entity Clock is
     port (stdby : in std_logic;
           osc_int: out std_logic
           );
end Clock;

architecture Clock_behav of Clock is

    COMPONENT OSCH
    -- synthesis translate_off
        GENERIC (NOM_FREQ: string := "2.56");
    -- synthesis translate_on
        PORT (STDBY : IN std_logic;
              OSC : OUT std_logic
                );
    END COMPONENT;
attribute NOM_FREQ : string;
attribute NOM_FREQ of OSCinst0 : label is "2.56";

begin

    Clock: OSCH
    -- synthesis translate_off
    GENERIC MAP( NOM_FREQ => "2.56" )
    -- synthesis translate_on
    PORT MAP (  STDBY => stdby,
                OSC => osc_int
    );

end Clock_behav;

Lattice Fpga Internal clock

1 Answers