I am wondering about one phenomenon I've seen during I2C tests.
I observe that when I write on address 0 from master to slave, the SDA line is put to high between two SCL ticks juste after the first byte (address + R/W bit) is sent. It doesn't change anything to the behavior but I would like to know why this is happening.
Note : On the image the address is 0 and I am writing 3 bytes 0x00. This is why everything is low on SDA line excepted my phenomenon.
Does anybody have a suggestion?
In I2C communication from the master to the slave, each transferred byte consists 8 data bits sent by the master and 1 acknowledge bit sent by the slave. So after bit 8, the master releases the SDA line so the slave can take control of it.
If there is a some delay between the master releasing SDA and the slave taking control, none of the two parties controls the line and it's pulled high by the mandatory pull-up resistors. That's what is visible on your oscilloscope.
This is perfectly fine as the SCL line is low. SDA is only sampled when SCL is high.
I can only speculate why it only occurs for the first byte. Possibly the slave takes some time to compare the received address and to decide if it is the addressed slave and has to respond. For later bytes, this is not needed anymore as the slave knows upfront it's part of an active I2C communication.
