In clock stretching, if the slave holds the clock line low, the master should wait to conclude about any ACK on the line. Since the slave can release the clock signal at any time, how do we interpret the SDA line value if the slave releases the clock, e.g. 3/4 of the way through the master's clock period? Let me illustrate with an example
- Consider an I2C master with a 100 kHz clock rate (10 us period).
- When the master is transmitting, there is a rising edge on SCL every 5 us.
- During the ACK period, assume the slave holds the SCL line low for the first 7.5 us of the ACK period
- At the 7.5 us assume the slave releases SCL while sending out SDA low.
- In this case the SCL line will be high for 2.5 us before going low again and then proceeding with its 10 us period.
- Further, assume the slave then allows SDA to go high before the next rising edge of SCL (i.e. it holds SDA low for less than 7.5 us)
- Which rising edge of SCL indicates the valid SDA value?
- Is it the first rising edge (where SCL only stays high for 2.5 us)?
- Or is it the 2nd rising edge that is part of a full SCL clock period (5 us low, followed by 5 us high)?
