In a verilog simulation, I will have to communicate with the 64K I2C EEPROM from Microchip. Every time for getting an ack from slave, I am driving my SDA to high impedance for a given clock period. Now, in order to get data from slave, should I have to follow the same for SDA? Simply, should the SDA ports have to be driven to high impedance state ?
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2 Answers
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In a physical I2C circuit, there are pull-up resistors that make SCL and SDA go high when their outputs are in their high impedance states. The Verilog equivalent to the pullup resistor is the TRI1. This will make the lines defined rather than floating when the signals are in their high impedance state.
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Generally speaking if the SDA line has the open-drain design you need not to put it to the high impedance state (and probably you can't), but you should set it to the logical '1'. But if it is a tri-state IO pin then yes, you should put it into high-impedance state as otherwise you may damage your circuits.
