How to test sequential components properly with VUnit testing library and using VHDL? I've been using it to test combinatorial components using wait for statements etc. Example of it here in my github repo.
Obviously I've to generate a clock signal with clk <= not clk after half_period; but how to wait for it? Do I write something like wait until rising_edge(clk). But if I want to advance clock by multiple clock cycles? Is there better way than copy above line multiple times?
If you're using VUnit you already have such a procedure available. VUnit ships with the OSVVM library for its randomization features but it also contains other stuff, for example WaitForClock. To enable OSVVM you need to add the following in your Python script.
ui = VUnit.from_argv()
ui.add_osvvm()
I usually have something along this
procedure walk (
signal clk : in std_logic;
constant steps : natural := 1) is
begin
if steps /= 0 then
for step in 0 to steps - 1 loop
wait until rising_edge(clk);
end loop;
end if;
end procedure;
Just make sure that if you wait for other signals you might need to re-synchronize with the clock.
For example
clk <= not clk after 5 ns;
...
wait for 1.5 ns;
-- This assignment will happen at 1.5 ns, not at a clock edge!
a <= '1';
walk(clk, 1);
-- If you need somethign happening at a clock edge and you're not sure of where in
-- time you are, might be worth synchronizing at the start
walk(clk, 1);
--
a <= '1';
walk(clk, 1);
a <= '0';
walk(clk, 0);
...
Hope this helps!
wait_for_clks(6,clk)- Tricky