Data being written on same address in multi-write port RAM

Question

I have 3 write ports and 1 read port in my RAM. All the ports work at same frequency. If my write ports write data at different addresses of memory then it is okay but what will happen if all the three write ports write data at sane address location. I know it will turn out in "undefined data" at that location. So what to do to prevent this situation. I can't merge all the write ports and make it one as it is working on same frequency. I have to keep all the write ports separate.

I was thinking of partitioning the memory according to the port i.e. 1st port will get access to some part of memory and 2nd port will get access to another part of memory and similarly 3rd. But I don't think it will work as there also will be some issues which can't be neglected. So can anyone tell me what to do to write data on memory having 3 ports working at same frequency?

If you don't want to arbitrate then you need to specify what behavior do you want to happen. Do you want to OR/AND all of the data together? Do you want port2 to have priority over port1, and port3 to have priority over both? Maybe you want three separate memories and you can handle the problem afterwards somehow? — serpixo
The memory has to be common and that is the problem. Can you suggest me any way where I can write data on different memories and make it one block of memory? — Payal

Oldfart Oldfart · Accepted Answer · 2019-04-24T08:44:20

There is no simple solution.

Most dual-port data is of the producer-consumer type so the read data pointer is always behind the write data pointer. A FIFO being a prime example of that.

If you really have multiple processes which can write to the same location, you have a problem. I strongly suspect you have designed your system wrong.

In Verilog you can check if the write addresses are the same and when they are the same, use an arbiter to let only one through at a time. You will then have "defined data". However you still will have a race condition as a CPU read can happen between any of the writes and pick up 'old' data.

Data being written on same address in multi-write port RAM

1 Answers