Creating a `RAM` chip in `Verilog` with single in/out data port

Question

I want to create a RAM chip in verilog to learn how Verilog, modern chips like RAM and EEPROM allow reading and writing to the chip over a single address port and a single data port.(Data port being the input and output port) I want to do the same thing in Verilog, and I think I need the inout type, but I don't know how it works. I google it, but all RAM examples I can find have a separate data write and data read port. Since the inout type requires both sides to be connected to a wire, I need to connect one wire from one side to a reg chosen by the address.(so no assign).But I don't know how to do that.

This is what I tried and doesn't work:

wire [7:0] a;
wire rw;// 0 if read, 1 if write
reg [7:0] mem [16];
initial begin
  if (rw == 1) begin
    #1 a = mem[0];// 0 would be the address wire, but excluding it for clarity
  end
  if (rw == 0) begin
    #1 mem[0] = a;// 0 would be the address wire, but excluding it for clarity
  end
end

Can anyone help?

Thanks

Oldfart Oldfart · Accepted Answer · 2019-08-11T07:41:15

all RAM examples I can find have a separate data write and data read port.

The reason is a combination of two facts:

A true bi-directional data bus would requires tri-state drivers.
FPGA or ASIC chips no longer have on-chip tri-state drivers.

The only place where a bi-directional data is possible is at I/O where you have tri-state pads.

Thus internally everybody will use the two data buses as any real memory will have at its core a separate read-data and write-data bus. Then at the edge (at the pads) they will switch to bi-directional mode.

To write your own Verilog bi-directional bus you should use tri-state signal assignments. Something along the line of:

inout[7:0] data_bus,

// This assignment is inside the memory model:
// Driving the read data out of the memory device
assign data_bus = mem_read ? mem_read_data : 8'hzz;


// This assignment is outside the memory model
// Driving the write data into the memory device
assign data_bus = mem_read ? 8'hzz : external_driver;

Creating a `RAM` chip in `Verilog` with single in/out data port

1 Answers