Pass Information From System verilog Testbench to a C++ Program Using pipes

Question

I want to be able to pass information from System Verilog testbench to a c++ program through a pipe. Is there a way to implement this.

from system verilog you can call a 'C' function using the DPI interface. The latter can do whatever you want. — Serge

dave_59 dave_59 · Accepted Answer · 2019-04-20T16:05:16

If you are running on Linux, you can a named pipe file and have your testbench write to it. Then you can use that file as input to your program.

But a much more efficient solution is using SystemVerilog's DPI to pass the information by linking your C++ program into the simulation.