Neither does not seem to have been asked in any forums I could find, nor could I find how to do this using the GHDL documentation. Apparently I don't have enough reputation to ask a GHDL question on SuperUser(they don't have the tags), so I have to ask here.
I am trying to simulate a DSP core, which contains several self-written vhdl cores as well as a few Xilinx coregen cores using GHDL. I have to admit, that I am fairly new to GHDL, but not new to VHDL. I know the logic of the core and testbench in question is sound, since it simulates well using ISim. The program has its limits however, which is why I want to try GHDL.
However, GHDL does appear to chicken out on simulating a Xilinx FIR compiler, due to a missing Filter file.
I am setting up my simulation environment using the Makefile snippets below
#GHDL CONFIG
GHDL_CMD = ghdl
GHDL_FLAGS = --ieee=synopsys --warn-no-binding
# vhdl filebase
SRCBASE = ../../../source
ISEBASE = /opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src
####################
# import all the necessary source files
# first the external libraries
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=unisim $(ISEBASE)/unisims/{,primitive/}*.vhd
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=ieee_proposed $(ISEBASE)/ieee_proposed/*.vhd
$(GHDL_CMD) -i $(GHDL_FLAGS) --warn-no-library --work=xilinxcorelib $(ISEBASE)/XilinxCoreLib/*.vhd
# then the components roughly in the right order
# (the order actually does not matter, since the analysis step generates the correct order)
mkdir work
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=work $(SRCBASE)/coregen/*.vhd
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=work $(SRCBASE)/pcie/pkg_types.vhd
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=work $(SRCBASE)/DSP/*.vhd
#finally the main testbench (could be merged with the above)
$(GHDL_CMD) -i $(GHDL_FLAGS) dsptop_tb.vhd
########################
# create the Make file (the binding warning is disabled due to the many generates in the xilinx core libraries)
# also analyzes the design and generates the correct hierarchy strcture
$(GHDL_CMD) -m $(GHDL_FLAGS) -fexplicit --work=work dsp_top_tb
# run the stuff
$(GHDL_CMD) -r $(GHDL_FLAGS) -fexplicit --work=work dsp_top_tb
as you can tell from the import statements, my source files are actually in a different directory, which does not bother GHDL however.
Up to the last statement, everything runs fine. However, upon running the last command I receive an error :
endfile with a non-opened file
from: xilinxcorelib.fir_compiler_v6_3(behavioral).fn_read_mif_file at fir_compiler_v6_3.vhd:1648
ghdl:error: error during elaboration
I believe the problem is that my FIR compiler is generated using the Xilinx FIR compiler and uses a COE file to specifiy the filter coefficients. The line where the error occurs actually opens the file specifying the filter coefficients. In the coregen generated VHDL file it is specified here
-- Configuration specification
FOR ALL : wrapped_decimator_7fold USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_coef_file => "decimator_7fold.mif", -- < Problematic file
My question is now : How do I make GHDL look for the file. I already copied it to the folder, where the run command is being run. As far as I can tell, I cannot import non-vhdl files for GHDL to recognize. So how can I simulate the FIR compiler generated filter using GHDL then?
I hope someone knows how to do this.
Thanks in advance!
