I am attempting a simple case question in a VHDL book. As you can understand from the source code, it sets the output value depending on input range. However, I couldn't observe my input, x, when I run the testbench using GHDL.
Is this because x is a character type? Should I ask on GHDL issues page (https://github.com/ghdl/ghdl/issues)?
Source code (q4_case.vhd):
entity q4_case is
port (
x : in character; -- input
character_class : out integer); -- output
end entity q4_case;
architecture behav of q4_case is
begin -- architecture behav
-- purpose: set output depending on range of input
-- type : combinational
-- inputs : x
-- outputs: character_class
process (x) is
begin -- process
case x is
when 'A' to 'z' => character_class <= 1;
when '0' to '9' => character_class <= 2;
when nul to usp | del => character_class <= 4;
when others => character_class <= 3;
end case;
end process;
end architecture behav;
Test bench (q4_case_tb.vhd):
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity q4_case_tb is
end entity q4_case_tb;
-------------------------------------------------------------------------------
architecture q4_case_tb of q4_case_tb is
-- component ports
signal x : character;
signal character_class : integer;
-- clock
signal Clk : std_logic := '1';
begin -- architecture q4_case_tb
-- component instantiation
DUT : entity work.q4_case
port map (
x => x,
character_class => character_class);
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
x <= 'b';
wait until Clk = '1';
wait until Clk = '0';
x <= 'F';
wait until Clk = '1';
wait until Clk = '0';
x <= dc3;
wait until Clk = '1';
wait until Clk = '0';
x <= usp;
wait until Clk = '1';
wait until Clk = '0';
x <= del;
wait until Clk = '1';
wait until Clk = '0';
x <= '0';
wait until Clk = '1';
wait until Clk = '0';
x <= '5';
wait until Clk = '1';
wait until Clk = '0';
x <= '9';
wait until Clk = '1';
wait until Clk = '0';
x <= '=';
wait until Clk = '1';
wait until Clk = '0';
x <= 'Ü';
wait until Clk = '1';
wait until Clk = '0';
report "End of simulation" severity failure;
end process WaveGen_Proc;
end architecture q4_case_tb;
-------------------------------------------------------------------------------
configuration q4_case_tb_q4_case_tb_cfg of q4_case_tb is
for q4_case_tb
end for;
end q4_case_tb_q4_case_tb_cfg;
-------------------------------------------------------------------------------
Compile and run commands:
ghdl -a q4_case.vhd
ghdl -a q4_case_tb.vhd
ghdl -r q4_case_tb --vcd=q4_case.vcd
Version information:
ghdl -v
GHDL 0.35 (tarball) [Dunoon edition]
Compiled with GNAT Version: GPL 2017 (20170515-63)
mcode code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2015 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Beginning of VCD output file is given below. As you can see, x is not handled and I can't observe x by viewing with GTKWave.
Part of VCD:
$date
Thu Feb 08 09:19:40 2018
$end
$version
GHDL v0
$end
$timescale
1 fs
$end
$comment x is not handled $end
$var integer 32 ! character_class $end
$var reg 1 " clk $end
$scope module dut $end
$comment x is not handled $end
$var integer 32 # character_class $end
$upscope $end
$enddefinitions $end
#0
b1 !
1"
b1 #
#10000000
...
...
signal char_pos: integer range 0 to 255;and an assignmentchar_pos <= character'pos(x);to display in gtkwave as decimal or ascii (noting non-graphic characters are shown with '.'). If you don't add x to the gtkwave waveform it won't crash. – user1155120