SystemVerilog interface - Passing parameters after module declaration

Question

Given the following module declaration:

module ( myinterface.mymodport mybus, ... );

And assuming that myinterface has parameters, how do I specify them?

The interface instantiation happens only in the testbench, but now I want to synthesize the DUT, so the TB disappears.

Answer 1

This is an oversight in the SystemVerilog LRM. There's no syntax to specify a required set of parameters for an interface in a module header.

You might check your synthesis tool to see if they provide any way of specifying parameter overrides for the top-level synthesis instance.

Answer 2

You specify the parameter when you instantiate the interface; you do not specify it in the port list of the module. Given

interface myinterface #(parameter DATA_SIZE = 0);
...

All you need is

module mymodule (myinterface.mymodport mybus);
...

because somewhere else you have

myinterface #(.DATA_SIZE(64)) i();

---

interface myinterface #(parameter DATA_SIZE = 0);
  logic [DATA_SIZE-1:0]  AWID;
  logic [31:0] AWADDR;
  modport mymodport (input AWID, AWADDR);
endinterface

module mymodule (myinterface.mymodport mybus);
  initial
    $display("mymodule");
endmodule

module top;
  myinterface #(.DATA_SIZE(64)) i();
  mymodule m (.mybus(i));
endmodule

https://www.edaplayground.com/x/528x