Verilog error signal has multiple drivers

Question

None of the answers I have found to question regarding multiple drives seem to apply to my situation so I will ask.

I have multiple clocks of the same frequency but shifted in time from one another.

I wish to create a signal based on changing its level at different positions within the period.

Simple case:

ClockA and ClockB - same frequency but B is shifted by X number of degrees relative to A.

wire Signal_On_Wire;

reg SigValue;

always @ (posedge Clock_A)
     SigValue<= 1'd0;

always @ (posedge Clock_B)
     SigValue<= 1'd1;

Assign Signal_On_Wire = SigValue;

In this example - the values don't matter - it just the fact that I want to drive SigValue from multiple clocks.

Verilog gives me a multiple driver error.

Is there any work-around to allow me to accomplish what I want to do?

Thanks

It would help to explain more about the environment around this. What other clock are involved in the signals you want to register, and on what clock edges do you expect to read the signal. Maybe there is an entirely different approach. — dave_59

Laleh Laleh · Accepted Answer · 2019-02-10T20:05:51

This one should work.

always @ (posedge clock_B) if (~sigValue) Flop <= ~Flop;

always @(posedge clock_A) if(sigValue) Flip <= ~Flip;

assign sigValue = Flop ^ Flip;

Remember to add reset to initialize Flip and Flop.

Verilog error signal has multiple drivers

1 Answers