Fixing "multiple drivers" errors in Verilog

Question

I have some code written in Verilog, simulation works well, but synthesis of course (what did I expect?) doesn't. I get an error about multiple drivers being used. Here is the basic code that will cause this error (not real code because that is ~300 lines at this point):

always @(posedge reset) begin
   A <= 0;
   B <= 0;
   C <= 0;
   ...
end

always @(posedge D) begin
   case (E)
     0: do something
     1: do something else
     2: begin C <= B; A <= 1; end 
     default: ...
end

always @(posedge A) begin
   B <= 1;
   A <= 0;
end

So the idea is I want to have essentially sequential code, but I'm not allowed to mix blocking and non-blocking code, so I have non-blocking statements. C <= B needs to happen before B <= 1, because I want C to have the old value of B. So I figured I would essentially insert a flag in the form of A to make changes to B once C acquired its value.

I don't know how to fix it. I also don't really understand the point of allowing multiple processes to exist at all (especially since simulation gives no warning about this being a problem), if they have to be 100% unrelated.

I understand that it cannot promise that posedge D and posedge A will not happen at the same time, but I know that they won't. Is there a way to tell the compiler that?

Thank you!

You can't drive a signal (A, B, C) in more than 1 always block. — Qiu

nmore nmore · Accepted Answer · 2014-08-14T21:13:03

I understand that it cannot promise that posedge D and posedge A will not happen at the same time, but I know that they won't.

Yes, but like you said, the compiler doesn't know that, and will complain. You have to make sure that you are not driving variables from multiple always blocks.

To do this, use case statements. For example:

always @(posedge clk) begin // or some common condition
  case (reset)
    0:
    // do stuff, and use nested case statements
    1:
    // reset
    ...
end

And just in case you don't know, you want to use case statements instead of if statements because the compiler can optimize the code better with case statements.

Fixing "multiple drivers" errors in Verilog

1 Answers