Verilog Multiple Constant Drivers

0
votes

I wrote a test program that will assign a pin to 1 when the positive edge of a signal is found, and to 0 when a negative edge of a different signal is found.

By using 2 always statements, I get the multiple constant drivers error. How can I edit my code so that I only use 1 always block and not get the error?

module clockedge(clock1, clock2, out);
input clock1;
input clock2;
output out;
reg out;

always@(posedge clock1) begin
    out=1;
end

always@(negedge clock2) begin
    out=0;
end

endmodule

I am compiling in Quartus II for a Cyclone II.

The errors that I get:

  • Error (10028): Can't resolve multiple constant drivers for net "out" at clockedge.v(11)
  • Error (10029): Constant driver at clockedge.v(7)
2
verilog
Well, it compiles OK in a simulator, which is what I would have expected: edaplayground.com/x/2Bhf. So, I guess you are trying to synthesise this. In which case, what hardware are you expecting to be synthesised? - Matthew Taylor
I added the errors and software I am using - Eric Johnson

2 Answers

2
votes

Maybe you could try:

    module clockedge(clock1, clock2, out);
    input clock1;
    input clock2;
    output out;
    reg out;

    always@(posedge clock1 or negedge clock2) 
    begin
    if (clock1 == 1) out=1; // Means after a posedge, clock1 should be 1
    if (clock2 == 0) out=0; // Means after a negedge, clock2 should be 0

    end
    endmodule
1
votes

What hardware are you expecting? I guess you might be able to come up with some asynchronous circuit that does this, but does it need to be asynchronous? Here is a synchronous circuit that does what you want:

module clockedge(clock, clock1, clock2, out);
  input clock;
  input clock1;
  input clock2;
  output out;

  reg out;
  reg clock1_d, clock1_dd, clock1_ddd;
  reg clock2_d, clock2_dd, clock2_ddd;
  wire up, dn;

  // I'd synchronise first...
  always@(posedge clock) begin
      clock1_d   <= clock1;
      clock1_dd  <= clock1_d;
      clock2_d   <= clock2;
      clock2_dd  <= clock2_d;
  end

  //...then we need synchronous edge detectors...
  always@(posedge clock) begin
      clock1_ddd <= clock1_dd;
      clock2_ddd <= clock2_dd;
  end
  assign up = ~clock1_ddd &  clock1_dd;
  assign dn =  clock2_ddd & ~clock2_dd;

  //..and here's an FSM that does the rest
  always@(posedge clock) begin
    if (up)
        out <= 1'b1;
      else
        if (dn)
          out <= 1'b0;
  end

endmodule

You'll probably want a reset, though.

http://www.edaplayground.com/x/3GGS