VHDL Error when converting std_logic_vector into unsigned integer

Question

I want to convert a 16-bit std_logic_vector into an integer to use it in a process realising a Moore machine.

entity steuerung is
  port (
    Clk            : in std_logic;
    Reset           : in std_logic;
    AktPos          : in std_logic_vector(15 downto 0);
    Notaus          : in std_logic; 
    Betrieb         : in std_logic; 
    HPR             : in std_logic;   
    HPL             : in std_logic;
    ESR             : in std_logic;
    ESL             : in std_logic;
    CntClr          : out std_logic;
    LedR            : out std_logic;    
    LedG            : out std_logic;        
    M_An            : out std_logic;
    M_Li            : out std_logic;
    M_Re            : out std_logic;
    State           : out std_logic_vector(5 downto 0)  
  );
end steuerung;

architecture BEHAVE of steuerung is
begin
  process (Reset, Clk, Notaus, Betrieb, AktPos, ESR, ESL) is
    type zustand is (steht, links, rechts, neuUnten, neuOben, alarm);

    variable zustands_vektor : zustand;
    variable ausgabe_vektor  : std_logic_vector(5 downto 0);
    variable cnt             : integer range 0 to 65535 := conv_integer(unsigned(AktPos));

But I'm getting a few errors concerning the last line of code. The console tells me the following:

"no declaration for "unsigned" no overloaded function found matching 'conv_integer'" and also a few errors in the std_logic_arith library (which I definitely included, although not seen in the code)

What have I done wrong?

Paebbels Paebbels · Accepted Answer · 2018-12-15T22:25:05

Your code and your question has many issues ... Here is a list of things to fix:

Use English identifiers for documentation reasons, so others then natives like me can read and understand your question and your code. Moreover you are mixing Germany and English identifiers in the same file.
Add the full code, so we can see the surrounding context. It's needed to investigate and explain your mistakes.
std_logic_arith is a package, not a library. IEEE would be a VHDL library.
Don't use package std_logic_arith. use package numeric_std instead.
When using package numeric_std, an unsigned value is converted to integer with to_integer:
cnt := to_integer(unsigned(AktPos));
The signals: Reset, Notaus, Betrieb, AktPos, ESR, and ESL don't belong to the sensitivity list of a clocked process.
The initial value assignment for your variable is executed only once. Probably, this isn't what you want to achieve, right?
Type zustand is an enumeration type. Thus, the variable zustands_vektor uses wrong naming for an object containing a scalar discrete value. A vector is an array.

In general, using variables in VHDL is nothing for starters. Most likely, you want to use signals. VHDL is a hardware description language not a programming language, where you use variables for daily problem solving.

VHDL Error when converting std_logic_vector into unsigned integer

1 Answers