I am having some trouble understanding why I am getting different results with the register module below.
module register (clk, rst, ld, din, dout);
input clk;
input rst;
input ld;
input [3:0] din;
output reg [3:0] dout;
always @(posedge clk or posedge rst) begin
if(rst) dout = 4'b0;
else if(ld) dout <= din;
else dout <= dout;
end
endmodule // rgister
module controller(clk, rst, ldI);
input clk;
input rst;
output ldI;
reg [2:0] ps, ns;
always @(posedge clk or posedge rst) begin
if(rst) ps <= 3'b0;
else ps <= ns;
end
always @(ps) begin
case(ps)
3'b000 : ns <= 3'b001;
3'b001 : ns <= 3'b010;
3'b010 : ns <= 3'b011;
3'b011 : ns <= 3'b100;
3'b100 : ns <= 3'b101;
3'b101 : ns <= 3'b110;
3'b110 : ns <= 3'b111;
3'b111 : ns <= 3'b000;
endcase // case (ps)
end // always @ (ps)
assign ldI = (ps == 3'b001) ? 1'b1 : 1'b0;
endmodule // reg_controller
module datapath (clk, rst, ldI, din);
input clk;
input rst;
input ldI;
input [3:0] din;
register Ireg (clk, rst, ldI, din);
endmodule
module top (clk, rst, din);
input clk;
input rst;
input [3:0] din;
wire ldI;
datapath dp (clk, rst, ldI, din);
controller cp (clk, rst, ldI);
endmodule // top
module tb;
reg clk, rst;
reg [3:0] din;
reg ld;
initial begin
rst = 1'b1;
clk = 1'b0;
din = 4'b0;
ld = 1'b0;
end
top uut (clk, rst, din);
register r (clk, rst, ld, din);
always #5 clk = ~clk;
initial begin
#21 rst = 1'b0;
din = 4'h1;
@(posedge clk);
din = 4'h2;
ld = 1'b1;
@(posedge clk);
ld = 1'b0;
din = 4'h3;
@(posedge clk);
din = 4'h4;
@(posedge clk);
din = 4'h5;
#50;
$finish;
end // initial begin
endmodule
Here is the wave output:
In the waves above, the blue is 'r' in the tb and the green is the Ireg in the datapath. I have stripped out most of what was in the datapath and controller to narrow down this timing problem that I am having.
I would like to have Ireg contain the value 2. What adjustments can I make to have this? I have tried using the negedge of the clock in the register module nad it works, but I don't feel this is the correct solution.
Thanks
