What is the relationship between the _mm_sfence intrinsic and a SFENCE instruction?

2
votes

I am experimenting with non-temporal instructions, and am already familiar with how fences with ordinary load/stores operate.

Intel defines an intrinsic, _mm_sfence, in relation with non-temporal operations, which the manual defines as:

Guarantees that every preceding store is globally visible before any subsequent store.

I have some questions about this operation.

  1. Is this just inserting a SFENCE instruction? If not, what does this translate to?
  2. If this is not just a SFENCE, does a SFENCE instruction also carry the ordering guarantee for non-temporal stores?
1
x86memory-barriers

1 Answers

5
votes

The _mm_sfence intrinsic does two things:

  • Inserts the SFENCE instruction.
  • Depending on the compiler, it inserts a compiler write barrier so that the compiler will not reorder any memory writes across the intrinsic with respect to program order. This is the case in GCC, MSVC, and ICC. Not sure about Clang though, but most probably it does that too.