Trouble with carry in ALU (Verilog)

Question

As an assignment, first made a 4 bit ALU with the regular, click and drag gates, etc. in ALtera Quartus. Now, we are implementing it using Verilog.

I have this 4x1 MUX:

module MUX_4x1(I0, I1, I2, I3, S1, S0, H);
    input I0, I1, I2, I3, S1, S0;
    output H;
    wire mux1, mux2;
    MUX_2x1 mux_1(I0, I1, S1, mux1);
    MUX_2x1 mux_2(I2, I3, S1, mux2);
    MUX_2x1 mux_3(mux1, mux2, S0, H);
endmodule

This Full Adder:

module Full_Adder(A, B, Cin, S, Cout);
    input A, B, Cin;
    output S, Cout;
    assign S = (A ^ B) ^ Cin;
    assign Cout = ((A ^ B) & Cin) | (A & B);
endmodule

And finally, the Arithmetic Unit for the ALU:

module AU(A3, A2, A1, A0, B3, B2, B1, B0, S1, S0, G3, G2, G1, G0, Carry, N, V);
  input A3, A2, A1, A0, B3, B2, B1, B0, S1, S0;
  output G3, G2, G1, G0, Carry, N, V;
  wire mux1W, mux2W, mux3W, mux4W, Cin, C0_out, C1_out, C2_out, C3_out;
  MUX_4x1 mux1(B0, !B0, 1'b1, 1'b1, S1, S0, mux1W);
  MUX_4x1 mux2(B1, !B1, 1'b0, 1'b1, S1, S0, mux2W);
  MUX_4x1 mux3(B2, !B2, 1'b0, 1'b1, S1, S0, mux3W);
  MUX_4x1 mux4(B3, !B3, 1'b0, 1'b1, S1, S0, mux4W);
  assign Cin = (!S1 & S0);
  Full_Adder fAdder1(A0, mux1w, Cin, G0, C0_out);
  Full_Adder fAdder2(A1, mux2w, C0_out, G1, C1_out);
  Full_Adder fAdder3(A2, mux3w, C1_out, G2, C2_out);
  Full_Adder fAdder4(A3, mux4w, C2_out, G3, C3_out);
  assign Carry = C3_out;
  assign N = G3;
  assign V = 1'b0;
endmodule

I have set V (Overflow) to be 0 just because it depends on the carry and carry is broken right now. I did a functional simulation and compared it to out previous Arithmetic Unit and the Carry is way off:

I can't figure out what is wrong with my code? I'm thinking maybe I need to do something with wires, but just cant figure it out.

please do not use images for the code. someone might want to cut and paste it to figure out your issues. With images you have less chance to get an answer. — Serge

Unn Unn · Accepted Answer · 2018-04-11T23:13:29

Assuming the code for your MUX_2x1 is correct, I notice two things about your code that might be the source of your error:

In your AU module, you have declared the mux outputs to be muxNW (like mux1W), but you use them in as an input to your Full_Adder as muxNw (mux1w) with a lower case 'w' instead of an upper case 'W'. Thus the net is not being connected correctly, since most tools will infer a wire if a variable is not explicitly declared. Add `default_nettype none to the top of all your files to avoid this behavior.
While without more information, I cant be sure, I think you have your S1 and S0 lines mixed up in your MUX_4x1. Typically, a S0 will select the LSb and S1 the MSb, so {S1, S0} is equal to the input number. For example, S1 = 1'b1 and S0 = 1'b0 would select I2 while in your current design it would select I1.

Another suggestion would be to use explicit port assignment. While you didnt make any mistakes I can see in the code you provided, using implicit connections is prone to errors. Example of using explicit connections:

Full_Adder fa1(.A(A), .B(mux1W), .Cin(Cin), .S(G0), .Cout(C0_out));

Trouble with carry in ALU (Verilog)

1 Answers