I am following the solution in GNU Makefile treating each recipe line as sub-shell command without continuation character
target_compile: PROJECT_SIM_OPTS += -LDFLAGS -L${CURRENT_DIR},-lm -load
target_compile: copy_shared_object actual_compile_with_sim_opts
@echo PROJECT_SIM_OPTS=${PROJECT_SIM_OPTS} ...
When I make the Makefile, I am able to see the second target_compile fire off but not the first target_compile which has no dependencies and recipe except a variable. I tried adding override before PROJECT_SIM_OPTS and ; at the end of the line but still it is not working.
There is no Error message reported which makes it even harder to detect. In nutshell, I have to embed this piece of code in another Makefile and if the first target would work, I will see a file generated with -LDFLAGS -L${CURRENT_DIR},-lm -load in it. Since this file is being generated without these flags, I am confident to say that first target is not firing.
How can the two target_compile work together?
PROJECT_SIM_OPTS=-LDFLAGS -L,-lm -load ...Can you confirm that you getPROJECT_SIM_OPTS= ...? Which version of Make are you using? - BetaGNU Make 4.0 Built for x86_64-unknown-linux-gnu- tulambaecho PROJECT_SIM_OPTS=${PROJECT_SIM_OPTS}. If that works, uncomment the compiler command but make sure the command itself is being echoed to the screen so that you can see what it actually is -- and interrupt the compilation, don't wait 40 minutes. - BetaPROJECT_SIM_OPTSis a global variable earlier in an included makefile while intarget_compile, which comes later, it is target specific variable. I see its value being printed in the file whenPROJECT_SIM_OPTSis a global variable but not when it is target specific variable. Any idea how to make its behavior like a global variable even in a target scope? - tulamba