Could you please help me to understand how GNU Make (version 3.81) processes simple Makefile? Here is the file:
.PHONY: a b c e f
a : b c
@echo "> a(b,c)"
e : a
@echo "> e(a)"
e : f
@echo "> e(f)"
f :
@echo "> f()"
b :
@echo "> b()"
c :
@echo "> c()"
Now I run command
make e
to build 'e' target. Make's output looks like:
Makefile:7: warning: overriding commands for target `e'
Makefile:5: warning: ignoring old commands for target `e'
> f()
> b()
> c()
> a(b,c)
> e(f)
http://www.gnu.org/software/make/manual/html_node/Error-Messages.html gives next explanation:
‘warning: overriding recipe for target `xxx'’
‘warning: ignoring old recipe for target `xxx'’
GNU make allows only one recipe to be specified per target (except for double-colon rules). If you give a recipe for a target which already has been defined to have one, this warning is issued and the second recipe will overwrite the first.
But from output we can see that commands for build 'a' target are also performed. I thought that according to description at 'Error-Messages' page make, while processing this Makefile and trying to build 'e' target (make e), should at first place decides that 'e' depends on 'a' and then overwrite this to 'e' depends on 'f'. And output should looks like:
Makefile:7: warning: overriding commands for target `e'
Makefile:5: warning: ignoring old commands for target `e'
> f()
> e(f)
But it looks like make still remember that 'e' depends on 'a' and not overwrite recipe at all.
Please help me to understand this behavior. Why are commands for building 'a' target still performed, even after recipe overwriting?
