GNU Makefile treating each recipe line as sub-shell command without continuation character

Question

I am trying to get the target_compile to work.

copy_shared_object:
    cp shared_object.so ${CURRENT_DIR}
    PROJECT_SIM_OPTS += -LDFLAGS -L${CURRENT_DIR},-lm -load

target_compile: copy_shared_object actual_compile_with_sim_opts

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actual_compile_with_sim_opts:
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I am getting the Error despite the fact that I have not added ;\ on the first line starting with cp

make: PROJECT_SIM_OPTS: Command not found
makefile:282: recipe for target 'copy_shared_object' failed
make: *** [copy_shared_object] Error 127

That's how gnu make works. What exactly is the second command supposed to do? It looks as if you're trying to modify a makefile variable PROJECT_SIM_OPTS. — G.M.
You're a little mixed up about what error you're seeing. It has nothing to do with continuation of the previous line. Remove the previous line (cd ...) entirely, and you'll get the same error. You're trying to manipulate a variable, using Make syntax, in a shell command, and the shell is complaining that your command makes no sense. What are you trying to do in the second line? — Beta
@Beta I am trying to pass in special flags that are needed in the actual compile. See the modified code above — tulamba
Pass them into the compiler? But you don't invoke the compiler in that rule. And shell variables don't survive the command. And shell commands can't modify Make variables. If you show us the rule that uses that variable (and enough of the makefile to constitute a minimal complete example), then maybe we can advise you. — Beta

HardcoreHenry HardcoreHenry · Accepted Answer · 2018-04-02T17:17:00

What you likely want is something like:

${CURRENT_DIR}/shared_object.so: shared_object.so
    cp $^ $@

target_compile: PROJECT_SIM_OPTS += -LDFLAGS -L${CURRENT_DIR},-lm -load

target_compile: copy_shared_object actual_compile_with_sim_opts
    @echo PROJECT_SIM_OPTS=${PROJECT_SIM_OPTS} ...

To explain a few things (and to reiterate @Beta's remarks): The variable ${CURRENT_DIR} is a makefile variable. It can come from either the environment or makefile. make will substitute the value for the variable name at its first phase (before it runs any rules). Therefore its value cannot be changed when running a rule. Makefile variables have a single $, and require braces around them if they're multi-character tokens.

${PROJECT_SIM_OPTS} is a target-specific makefile variable. It's still a makefile variable, so it cannot change its value when the make is executing the rules. That being said, its value is specific to the target_compile rule, and any rule that is being run as a result of that rule.

For shell variables, it's possible to set a value within a recipe, however, the scope of that value is that recipe line itself. In order to use shell variables you need to do $$shellvarname (with two $'s, as make expands $$ to $ before invoking the shell) That being said, each line of a recipe is run in a subshell, and any variable values will not be visible in other subshells. So, for example, if you have:

target: prereq
     @shellVar="value"; echo "recipe1: shellVar is $$shellVar"
     @echo "recipe2: shellVar is $$shellVar"

it will output:

recipe1: shellVar is value
recipe2: shellVar is

as recipe1's subshell does not communicate with recipe2's subshell, and therefore recipe2 is not aware of recipe1's value for the variable.

GNU Makefile treating each recipe line as sub-shell command without continuation character

1 Answers