How to add verilog synthesis directives in Chisel3?

Question

For example, I need to make sure a register array is synthesized with block RAM, then in Verilog:

reg [3:0] my_ram [255:0] /* synthesis syn_ramstyle=block_ram */;

How can I code the similar in Chisel?

Thanks very much.

Jack Koenig Jack Koenig · Accepted Answer · 2017-12-28T00:10:22

Sadly this currently is not supported. There is an existing feature request on the Firrtl repo: https://github.com/freechipsproject/firrtl/issues/687. We hope to add support for this in the not-so-distant future.