How to perform gate level simulation in Chisel3?

4
votes

I wrote a hardware design in Chisel3 and also wrote a testbench in Chisel3 to test the design.

And then, I synthesized the Verilog code which is generated by Chisel with Design Compiler. I want to verify that the behavior of RTL and Gate-Level are match. How can I co-simulate the synthesized Verilog Netlist and the original Chisel testbench ?

Is there a simple way to simulate the generated Verilog Netlist without rewriting a Verilog testbench ?

1
verilogchisel

1 Answers

2
votes

Unfortunately the Chisel testers do not provide a good way to do this. I will bring this up in the next Chisel developers meeting, but I also would suggest filing a feature request since this is clearly a very important missing feature.