Icarus Verilog simulation : Scope index expression is not constant: i

Question

I am simulating a 16 bit MIPS netlist in Icarus Verilog. This is the error i get in testbench

mips_16_core_top_tb_0.v:144: error: Scope index expression is not constant: i
mips_16_core_top_tb_0.v:144: error: Unable to bind wire/reg/memory `uut.register_file_inst.reg_array[i]' in `mips_16_core_top_tb_0_v.display_all_regs'

Related code : 
task display_all_regs;
begin
$display("display_all_regs:");
$display("------------------------------");
$display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
for(i=0; i<8; i=i+1)
$write("%d\t",uut.register_file_inst.reg_array[i]); <--- error points to this line

$display("\n------------------------------");
end
endtask

I do get this same error when i simulate the RTL too but i still get the vcd file dumped out.In case of the netlist,I dont even get the vcd file generated. Would be glad to hear your thoughts.

How is reg_array defined? Please define integer i; within the task. There might be conflicting drivers to the same i. — Greg
tried adding integer i; it says syntax error at line integer i; Error mips_16_core_top_tb_0.v:140: syntax error mips_16_core_top_tb_0.v:140: error: malformed statement — user2548629
Move integer i; before begin. You cannot attach the file here directly. You can upload it to a file sharing site with public access (or your own personal site) and provide the link. — Greg
If reg_array isn't defined how do you expect to write out its contents? Have you verified that the hierarchical path to the register values is the same in the netlist as it is in the RTL? — user1619508
Sorry for the confusion. The reg_array is a register declared in register_file.v.It is not an input/output port.Is this a syntactically correct way to call a signal that is not a part of the port declaration list?. — user2548629

EML EML · Accepted Answer · 2013-07-12T14:07:33

Your code looks fine, and I've just tested cross-module variable indexing of arrays in Icarus (the current version, from git) and it works.

I suspect your problem is that you're compiling mips_16_core_top_tb_0.v by itself - Icarus will give this message if you do. All source files need to be compiled together in Icarus. Some other simulators will allow you to compile this file by itself, and then only check for errors during elaboration (ie. when you run the simulation), but the way Icarus does it is how Verilog was originally intended to be used.

Icarus Verilog simulation : Scope index expression is not constant: i

2 Answers