I implement SIPO shift register by using verilog, but unknown error comes out

Question

Main file

module D_ff (q, D, Clk, Reset);
    input Clk, D, Reset;
    output q;
    always @ (posedge Clk);
        and(q, D, Reset);
endmodule

module SIPO(Clk, Reset, Data, Out1, Out2, Out3, Out4);
    input Clk, Reset, Data;
    output Out1, Out2, Out3, Out4;
    begin
    D_ff sr0 (Out0, Data, Clk, Reset);
    D_ff sr1 (Out1, Out0, Clk, Reset);
    D_ff sr2 (Out2, Out1, Clk, Reset);
    D_ff sr3 (Out3, Out2, Clk, Reset);
    end
endmodule

Testbench file

 'timescale 1ps/1ps

    module tb_SIPO;
        reg Clk, Reset, Data;
        wire Out1, Out2, Out3, Out4;

        SIPO(Clk, Reset, Data, Out1, Out2, Out3, Out4);

        initial
        Clk=0;  
        always #11 Clk=~Clk;
        Reset=1; Data=0;
        initial begin
            #15 Reset=1; Data=1;
            #20 Reset=1; Data=0;
            #30 Reset=1; Data=0;
            #10 Reset=0; Data=1;
            #20 Reset=0; Data=0;
            #5 Reset=0; Data=0;
            #20 Reset=0; Data=0;
            #20 Reset=0; Data=0;
            #20 Reset=0; Data=0;
            #20 Reset=0; Data=0;
            #70 Reset=0; Data=0;
            #5 $finish;
        end

    endmodule

Error: (vlog-13053) C:/Modeltech_pe_edu_10.4a/examples/tb_sipo.v(1): near >"'t": Illegal base specifier in numeric constant.

** Error: (vlog-13069) C:/Modeltech_pe_edu_10.4a/examples/tb_sipo.v(1): near >"'t": syntax error, unexpected BASE, expecting class.

I don't know what the error means. there is no 't' in my program and I can't see any illegal base specifier. What's wrong with this?

Qiu Qiu · Accepted Answer · 2017-12-08T07:42:44

You've used timescale for specifying the reference time unit for the simulator. But it should be:

`timescale

and not:

'timescale

' is used to specify numbers in Verilog, e.g. 8'hFF. That's why compiler is looking for a numeric constant.

I implement SIPO shift register by using verilog, but unknown error comes out

1 Answers