Use tasks in always @* blocks

Question

I was intended to use a customized task in an always @* block, like:

input [31:0] a;
input b;
output reg [31:0] c;

task mytask;
begin
    if (b) begin
        c = a;
    end
end
endtask

always @* begin
    // ... (b is not included)
    mytask;
    // ... (b is not included)
end

What I think is that when signal b changes from 0 to 1, c will be set to the content of a. Then I found the always block is not sensitive to signal b (using ISim 14.7).

Is this a bug or designed to behave like this?

Oldfart Oldfart · Accepted Answer · 2017-12-06T13:14:05

That is the defined behavior in Verilog. If you wan to make the task sensitive to the signals you have to put them in the I/O list:

task mytask(input b);

(And the reason I know is that I also made that error and looked it up)

Use tasks in always @* blocks

3 Answers